1. Field of the Invention
The present invention relates to a buffer first circuit and, more particularly, a buffer circuit used in a semiconductor device operating by different supply potentials and a method of operating the same.
2. Description of the Background Art
FIG. 8 is a circuit diagram showing a structure of a conventional output buffer circuit used in an EPROM (Erasable and Programmable Read Only Memory).
The output buffer circuit shown in FIG. 8 comprises a P channel MOSFET 1 connected between an output terminal 10 and the supply potential Vcc, an N channel MOSFET 3 connected between the output terminal 10 and the ground potential, a NAND gate 5 for driving the P channel MOSFET 1 and a NOR gate 7 for driving the N channel MOSFET 3. An internal data signal Din is applied to one input terminal of the NAND gate 5 and the NOR gate 7 through an input terminal 9. An output control signal oe is applied to the other input terminal of the NAND gate 5 and an output control signal oe is applied to the other output terminal of the NOR gate 7. A plurality of output buffer circuits are usually provided in the EPROM corresponding to the number of bits of data.
Next, a description is given of operation of the output buffer circuit shown in FIG. 8 in reference to FIG. 9.
In a normal reading, the supply potential Vcc is set at 5 V. First, it is assumed that the output control signals oe and oe are at logical high, or "H" level and logical low, or "L" level, respectively. In this case, when the internal data signal Din is at the "H" level the output of the NAND gate 5 becomes the "L" level and the output of the NOR gate 7 also becomes the "L" level. Then, the P channel MOSFET is rendered to be conductive and the N channel MOSFET3 is rendered to be non-conductive. As a result, output data Dout at the "H" level appears on an output terminal 10. On the other hand, when the internal data signal Din is at the "L" level, the output of the NAND gate 5 becomes the "H" level and the output of the NOR gate 7 becomes also the "H" level. Then, the P channel MOSFET 1 is rendered to be non-conductive and the N channel MOSFET 3 is rendered to be conductive. As a result, the output data Dout at the "L" level appears on the output terminal 10.
Next, it is assumed that the output control signal oe and oe are at the "L" level and the "H" level, respectively. In this case, the output of the NAND gate 5 becomes the "H" level and the output of the NOR gate 7 becomes the "L" level even if the output data signal Din is at either the "H" level or the "L" level. Then, both P channel MOSFET 1 and N channel MOSFET 3 are rendered to be non-conductive and the output terminal 10 becomes the floating state (the high impedance state).
For example, the above-described eight output buffer circuits are provided in the EPROM in which 8-bit data is read and sixteen output buffer circuits are provided in the EPROM in which 16-bit data is read. In a normal reading, it is necessary for all output buffer circuits to operate stably at high speed.
In data programming to the EPROM, data is programmed in units of one byte or several bytes. In order to verify whether the data is normally programmed or not, data is read from the EPROM. This operation is called "program verify".
FIG. 10 is a sectional view of a memory transistor comprised in the EPROM. The memory transistor comprises a source 12 and a drain 13 formed of an N.sup.+ layer formed on a P type semiconductor substrate 11, a floating gate 14 and a control gate 15.
In data programming, a supply potential Vpp for programming is applied to the control gate 15. The supply potential Vpp for programming is set at 12.5 V. At this time, the source 12 is set at 0 V and the drain 13 is set at approximately 8 V. In addition, in data reading, a supply potential Vcc is applied to the control gate 15. At this time, the voltage of the source 12 becomes 0 V and the voltage of the drain 13 becomes approximately 1 V. Although the supply potential Vcc is set at 5 V in normal reading, it is set at 6.about.6.5 V at the time of the "program verify".
FIG. 11 is a diagram showing the relation between a drain current I.sub.D and a gate voltage V.sub.G of the control gate of the memory transistor. Data "0" or data "1" is stored in this memory transistor depending on whether electrons are stored in the floating gate 14 or not. More specifically, when electrons are stored in the floating gate 14 by the above-described programming operation, the threshold voltage of the memory transistor is increased. Therefore, when the supply potential Vcc is applied to the control gate 15, a path between the source 12 and the drain 13 is rendered to be non-conductive. This state shows that the data "0" is stored in the memory transistor. On the contrary, when electrons are extracted from the floating gate 14, the threshold voltage of this memory transistor is decreased. Therefore, when the supply potential Vcc is applied to the control gate 15, a path between the source 12 and the drain 13 are rendered to be conductive. This state shows that the data "1" is stored in the memory transistor. In addition the data "0" is stored in the memory transistor by programming operation and the data "1" is stored in the memory transistor by erasing operation.
At the time of the "program verify", the reason why the supply potential Vcc is set at a potential higher than 5 V at the time of normal reading is to verify that the data "0" is programmed in the memory transistor with sufficient margin. More specifically, when the normal programming to the memory transistor is performed, the threshold voltage of the memory transistor becomes sufficiently higher than the read voltage V.sub.R as shown in FIG. 11. Therefore, by increasing the supply potential Vcc applied to the control gate 15 to perform reading operation, it can be verified whether the reading operation is performed with sufficient margin or not.
However, in the above-described conventional output buffer circuit, when the supply potential Vcc is increased at the time of the "program verify", an output charging/discharging current, a through current and the like are increased as compared with the time the supply potential Vcc is at 5 V. As shown in FIG. 12, load capacitance C is coupled between the output terminal 10 and the ground potential, and inductance L exists in a wiring between the N channel MOSFET 3 and the ground potential. For example, when the N channel MOSFET 3 turns on, an electric charge in the load capacitance C is discharged through the inductance L. At this time, a voltage v shown in the following equation is generated in the inductance L. EQU v=L.multidot.(di/dt)
where i represents a current and t represents a time period. Therefore, a noise will be generated in the ground potential. As can be understood from the above equation, as the current is increased, the noise is also increased.
Since a plurality of output buffer circuits are provided especially in the EPROM, it is necessary to consider the influence of the noise generated when the supply potential Vcc is increased.
As described above, there is a disadvantage that a switching noise is increased at the time of the "program verify" which increases and operates the supply potential Vcc in the conventional output buffer circuit as compared with the time of normal reading operation, with the results that stable operation of the "program verify" is prevented.
In addition, a page programming mode is started to be used in 1M bit of EPROM. In this page programming mode 2-word data to be programmed is latched in the inside once, and the latched 2 word data is programmed at the same time. Therefore, there is another disadvantage that the contents of the latch data would be destroyed if the noise generated at the time of the "program verify" is larger.